David T. Ellis, Ball Aerospace; Chris Daywalt, Ball Aerospace
Keywords: Onboard processing, SDA algorithms, feedback control, tracking
Abstract:
Closed Loop Pointing and Tracking
To enable effective onboard, automated tracking as part of an integrated tasking loop, closed loop tracking algorithms are necessary to engage pointing hardware such as gimbals, steering mirror assemblies, or body-pointed spacecraft adjustments. For mission flexibility, Ball has developed and demonstrated a modular software architecture for closed loop detection, tracking, and pointing allowing for regular updates to the code base for active mission tuning.
Modular Software Architecture
Our focus is to develop a software architecture that enables plug and play closed loop feedback pointing and tracking control. This capability is achieved by defining and implementing the APIs needed on either side of the data processing software. By defining the interfaces for the data processing software, the software may be changed later changed without affecting either the FPGA portion of the data processing or the down-stream information collected by the host. This enables machine learning (ML) to replace the software algorithms.
Abstracting a payload is a multi-level process and occurs both between components and within components. At the highest (and simplest) abstraction, a payload with on-board processing and closed-loop control has 3 major components:
Sensor
Data Processing
Control
Each component in the process feeds data into the next component. At any point in this closed loop, data may be accessed for dissemination to a different component. Information external to the closed loop may also be needed to support the functionality of the process.
There are multiple layers and types of abstraction that may be achieved within the sensor-data processing-closed-loop control process. Each of these is examined to achieve a more cost-effective and lower-risk development schedule that allows the Systems and Software teams to focus on the mission specific capabilities. Using APIs and abstracted components enables development teams to start with software environments that already contain reused components, generic models/placeholders, and hardware that can be interfaced via abstracted data and control paths.
Modular Hardware Architecture: Heterogeneous On-Orbit Processing Engine (HOPE)
To realize the goals of the HOPE system, an architecture for hardware and software has been created which is broken into two distinct units: the rad-hard core system and the experimental system. These two systems are co-located together in a chassis and share a backplane; however, the experimental system is designed for reconfiguration and testing of various processing elements while the rad-hard system is a static configuration that manages the experiments. Figure 2 shows a notional system block diagram.
Figure 2. Block Diagram of HOPE Architecture
The basic premise of the electrical architecture is to provide a standard set of radiation-tolerant services which can interface with any configuration of experimental boards. This is accomplished with three key pieces of technology. The first is an active backplane with intelligent power monitoring and control features, the second is the rad-hard supervisor single-board computer (SBC) running experiment management software, and the third is an FPGA-based high-speed data router with protocol translation. The HOPE backplane will be based on the ANSI/VITA 78-2015 SpaceVPX standard which supports popular space data protocols such as Serial Rapid IO (SRIO) and SpaceWire, and adds redundancy to the utility plane for improved fault tolerance. Additionally, the HOPE backplane may include support for the ANSI/VITA 65-2019 OpenVPX standard to maximize compatibility with space and commercial VPX boards currently under development. VPX provides both connector and electrical interconnect specifications and supports both 3U and 6U board configurations. The initial HOPE assembly will use the 100mm×160mm 3U form factor. Main system power is achieved in two ways. For laboratory experiments, regulated power can be applied directly to the backplane with a simple connectorized cable, allowing for many different total power scenarios without needing to define current and voltage power requirements. For spaceflight scenarios, the final hardware configuration will be known and a flight LVPS can be specified and procured based on specific mission needs. Of particular interest for HOPE is the ability to run different protocols over the standard-specific physical planes to enable integration of a variety of processor boards. Due to the use of COTS type processors, the radiation environment must be assessed for each space mission utilizing this architecture. There is a potential need for updated chassis designs or spot shielding based on expected performance of each COTS device. The risk posture of each program, orbit, service life, and other specific factors must be accounted for as well. The current design focuses on a lab-based demonstration to show the usefulness of the architecture in general, so research into more specific radiation requirements should be done at a later time.
Date of Conference: September 14-17, 2021
Track: SSA/SDA